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The effect of oxide thickness (EOT) on GaN-based double gate (DG) MOSFETs have been explored for low power switching device. The gate length (LG) of 8 nm with 4 nm underlap is considered. The device is turned off and on for gate voltage (VGS) of 0 V and 1 V, respectively. The effective oxide thickness (EOT) is varied from 1 nm to 0.5 nm and the device performance is evaluated. For EOT = 0.5 nm, the OFF-state current (IOFF), subthreshold slope (SS) and drain induced barrier lowering (DIBL) are obtained 2.97×10-8 A/μm, 69.67 mV/dec and 21.753 mV/V, respectively. These results indicate that, it is possible to minimize short channel effects (SCEs) by using smaller value of EOT.
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