Design of a Robust ESD Protection Device using 6H-SiC Nano-Scale GGNMOS

Abstract

—With the continuous shrinking of the
technological nodes and the introduction of new device concepts
and materials, integrated circuits (IC) are becoming more
vulnerable to electrostatic discharge (ESD) induced failures
which is one of the major concerns in designing robust ICs.
Therefore, to improve the reliability of the ICs against ESD
induced failures, extensive research efforts are being conducted.
In this paper, we have presented a 6H-SiC based nano-scale
grounded-gate NMOS (ggNMOS) ESD protection device and
compared the results with the 3C-SiC-based ggNMOS. To
design a robust ESD protection device, some critical device
parameters, such as substrate doping concentration,
source/drain doping concentration, drain to substrate contact
spacing, and substrate contact resistance should be optimized.
The ESD protection characteristics can be improved by utilizing
the near punch-through effect. It was found that the trigger
voltage and hold voltage are higher in 6H-SiC than the 3C-SiC
having identical device parameters. 6H-SiC shows better voltage
clamping performance as the turn-on resistance of 6H-SiC is
smaller compared to the 3C-SiC material. Therefore, the results
show that 6H-SiC has a better performance compared to 3C-SiC
and due to its higher bandgap, and can be used as a good ESD
protection device. All the simulations are carried out using the
Silvaco ATLAS device simulator.