Temperature Characteristics of Nano-Dimensional FinFET with P Type GaP Semiconductor Channel Based on ION/IOFF and Subthreshold Swing (SS)
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Abstract
This study discusses the effects of working temperature on the GaP-FinFET structure. Using the Multi-Gate Field Effect Transistors (MuGFET) simulation tool, the properties of FinFET have been generated over a temperature range of T=0 °C to T=125 °C. First, the structure of P-channel GaP-FinFET with such temperature vary and constant channel Fin parameters are simulated to find their current-voltage characteristics. The higher ΔI at the applied voltage inside the -0.7 to -1 V gate voltage range of the P-channel GaP-FinFET work as a temperature sensor in nano dimensions. The highest ∆I and sensitivity of temperature for P-channel GaP-FinFETs happen at Vg=-1 V, although the SS and ION/IOFF deteriorate as the working temperature rises.
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References
[2] C. Liu, H.-C. Sagong, H. Kim, S. Choo, H. Lee, Y. Kim, H. Kim, B. Jo, M. Jin, J. Kim, S. Ha, S. Pae and J. Park, “Systematical study of 14nm FinFET reliability: From device level stress to product HTOL”, IEEE Interna-tional Reliability Physics Symposium, P. 2F.3.1 - 2F.3.5, 2015.
[3] W. Lu, J. K. Kim, J. F. Klem, S. D. Hawkins and J. A. del Alamo, “An InGaSb p-channel FinFET”, IEEE In-ternational Electron Devices Meeting (IEDM), P. 31.6.1 - 31.6.4, 2015.
[4] Y. Hashim, "Temperature effect on ON/OFF current ratio of FinFET transistor," 2017 IEEE Regional Sympo-sium on Micro and Nanoelectronics (RSM), pp. 231-234, 2017.
[5] A. Raj et al., "GaN/AlGaN superlattice based E-mode p-channel MES-FinFET with regrown contacts and >50 mA/mm on-current," 2021 IEEE International Electron Devices Meeting (IEDM), pp. 5.4.1-5.4.4, 2021.
[6] J. Gu et al., "Narrow Sub-Fin Technique for Sup-pressing Parasitic-Channel Effect in Stacked Nanosheet Transistors," in IEEE Journal of the Electron Devices So-ciety, vol. 10, pp. 35-39, 2022.
[7] Y. Hashim, and O. Sidek, “Effect of temperature on the characteristics of silicon nanowire transistor”, Journal of nanoscience and nanotechnology, Vol. 12, No. 10, PP. 7849-7852, 2012.
[8] Y. Hashim, and O. Sidek, “Temperature effect on IV characteristics of Si nanowire transistor”, IEEE Colloqui-um on Humanities, Science and Engineering (CHUSER), PP. 331-334, 2011.
[9] Yasir Hashim, “Temperature Characteristics of 10nm N- and P-Channel Si-FinFET Structure”, International Conference on Electrical Engineering, Computer and In-formation Technology (ICEECIT), pp. 104-107, 2023.
[10] S. Kim et al., "MuGFET," Nanohub, 2014, [Online]. Available: https://nanohub.org/resources/NANOFINFET.
[11] C. -H. Shen, Y. Li, I. -H. Lo, P. -J. Lin and S. -C. Chung, "Modeling temperature and bias stress effects on threshold voltage of a-Si:H TFTs for gate driver circuit simulation," 2011 International Conference on Simulation of Semiconductor Processes and Devices, pp. 251-254, 2011.