Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder

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Muhammad Saddam Hossain
Farhadur Arifin


Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso. Power consumption and delay in the proposed 32-bit CSA found 322.6 (uW) and 0.556 (ns) whereas power and delay in the conventional 32-bit CSA was 455.4 (uW) and 0.667 (ns) respectively. We have done all the simulation using Cadence Virtuoso 90 nm tool.

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How to Cite
Hossain, M. S., & Farhadur Arifin. (2021). Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder. AIUB Journal of Science and Engineering (AJSE), 20(2), 1 - 7. Retrieved from
Author Biography

Farhadur Arifin, American International University-Bangladesh (AIUB)

Associate Professor, Department of Electrical and Electronics Engineering


[1] A. Amouri, F. Arifin, F. Hannig and J. Teich, "FPGA implementation of an invasive computing architecture," 2009 International Conference on Field-Programmable Technology, Sydney, NSW, 2009, pp. 135-142.
[2] T. Osman, S. S. Psyche, J. M. Shafi Ferdous and H. U. Zaman, "Intelligent traffic management system for cross section of roads using computer vision," 2017 IEEE 7th Annual Computing and Communication Workshop and Conference (CCWC), Las Vegas, NV, 2017, pp. 1-7.
[3] M. Hasan, M. H. Anik and S. Islam, "Microcontroller Based Smart Home System with Enhanced Appliance Switching Capacity," 2018 Fifth HCT Information Technology Trends (ITT), Dubai, United Arab Emirates, 2018, pp. 364-367.
[4] F. Arifin, R. Membarth, A. Amouri, F. Hannig and J. Teich, "FSM-controlled architectures for linear invasion," 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Florianopolis, 2009, pp. 59-64.
[5] M. Alioto, "Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 1, pp. 3-29, Jan. 2012.
[6] J. Warnock et al., "Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module," in IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 9-18, Jan. 2014.
[7] M. Hasan, M. H. Anik, S. Chowdhury, S. A. Chowdhury, T. I. Bilash, S. Islam, Low-Cost Appliance Switching Circuit for Microcontroller-Controlled Smart Home, International Journal of Sensors and Sensor Networks, vol. 2, no. 7, pp. 16-22, 2019.
[8] M. Li et al., "Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 12, pp. 3119-3123.
[9] S. Roy, M. Choudhury, R. Puri and D. Z. Pan, "Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 5, pp. 820-831, May 2016.
[10] T. F. Tay and C. Chang, "A new unified modular adder/subtractor for arbitrary moduli," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 53-56.
[11] E. Antelo, P. Montuschi and A. Nannarelli, "Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 409-418, Feb. 2017.
[12] M. Hasan, U. K. Saha, M. S. Hossain, P. Biswas, M. J. Hossein and M. A. Z. Dipto, "Low Power Design of a Two Bit Mangitude Comparator for High Speed Operation," 2019 International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, Tamil Nadu, India, 2019, pp. 1-4.
[13] S. K.C., S. M., G. B.C., L. D.M., Navya and P. N.V., "Performance Analysis of Parallel Prefix Adder for Datapath Vlsi Design," 2018 Second International Conference on Inventive Communication and Computational Technologies (ICICCT), Coimbatore, 2018, pp. 1552-1555.
[14] M. Hasan, M. J. Hossein, U. K. Saha and M. S. Tarif, "Overview and Comparative Performance Analysis of Various Full Adder Cells in 90 nm Technology," 2018 4th International Conference on Computing Communication and Automation (ICCCA), Greater Noida, India, 2018, pp. 1-6.
[15] K. A. K. Maurya, Y. R. Lakshmanna, K. B. Sindhuri and N. U. Kumar, "Design and implementation of 32-bit adders using various full adders," 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore, 2017, pp. 1-6.
[16] Wei Hwang, G. Gristede, P. Sanda, S. Y. Wang and D. F. Heidel, "Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability," in IEEE Journal of Solid-State Circuits, vol. 34, no. 8, pp. 1108-1117.
[17] K. Papachatzopoulos and V. Paliouras, "Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2546-2559, July 2019.
[18] V. Pudi and K. Sridharan, "Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA," in IEEE Transactions on Nanotechnology, vol. 11, no. 1, pp. 105-119, Jan. 2012.
[19] S. Khan and Z. A. Jaffery, "Parallel-prefix modulo adders: A Review," 2017 14th IEEE India Council International Conference (INDICON), Roorkee, 2017, pp. 1-5.
[20] R. Zlatanovici, S. Kao and B. Nikolic, "Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example," in IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 569-583, Feb. 2009.
[21] B. Ramkumar and H. M. Kittur, "Low-Power and Area-Efficient Carry Select Adder," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb. 2012.
[22] R. Mahalakshmi and T. Sasilatha, "A power efficient carry save adder and modified carry save adder using CMOS technology," 2013 IEEE International Conference on Computational Intelligence and Computing Research, Enathi, 2013, pp. 1-5.
[23] S. Patel, B. Garg, A. Mahajan and S. Rai, "Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems," 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Rourkela, India, 2019, pp. 300-303.
[24] J. Asha and J. Senthilkumar, "High speed Manchester Carry chain with carry-skip capability," 2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015], Nagercoil, 2015, pp. 1-7.
[25] M. Hasan, M. S. Islam, M. R. Ahmed, “Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms,” Science Journal of Circuits, Systems and Signal Processing, vol. 8, no. 2, pp. 76-81, 2019.
[26] C. Efstathiou, Z. Owda and Y. Tsiatouhas, "New High-Speed Multioutput Carry Look-Ahead Adders," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 10, pp. 667-671, Oct. 2013.
[27] O. Akbari, M. Kamal, A. Afzali-Kusha and M. Pedram, "RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 8, pp. 1089-1093, Aug. 2018.
[28] S. Ghafari, M. Mousazadeh, A. Khoei and A. Dadashi, "A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 157-162.
[29] N. J. Lisa and H. M. H. Babu, "Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming," 2015 28th International Conference on VLSI Design, Bangalore, 2015, pp. 238-243.
[30] H. M. H. Babu, L. Jamal and N. Saleheen, "An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder," 2013 IEEE International SOC Conference, Erlangen, 2013, pp. 98-103.
[31] W. Cheng, J. Hu, “A structured approach for optimizing 4-bit carry look-ahead adder,” The Open Electrical and Electronic Engineering Journal, vol. 8, pp. 133-142, 2014.
[32] S. J. Gladwin, M. Mangayarkkarasi, Design and performance comparison of 4-bit adders using different logic styles, Journal of Computational and Theoretical Nanoscience, vol 15, no. 3, pp. 949-960, 2018.
[33] M. Valinataj, Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors, Microelectronics Reliability, vol. 55, no. 12, pp. 2845- 2857, 2015.
[34] N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed. Delhi, India: Pearson Education, 2010.
[35] R. H. V and S. Hiremath, "Low Power Design and Implementation of Multi-Output Carry Look-Ahead Adder," 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, 2018, pp. 1912-1916.
[36] M. Hasan, P. Biswas, M. S. Alam, H. U. Zaman, M. Hossain and S. Islam, "High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder," 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Kanpur, India, 2019, pp. 1-5.
[37] M. Binggeli, S. Denton, N. S. Muppaneni and S. Chiu, "Optimizing carry-lookahead logic through a comparison of PMOS and NMOS block inversions," 2015 IEEE International Conference on Electro/Information Technology (EIT), Dekalb, IL, 2015, pp. 641-646.
[38] G. A. Ruiz, M. Granda, “An area-efficient CMOS carry-select adder based on a compact carry look-ahead unit,” Microelectronics Journal, vol. 35, no. 12, pp. 939-944, 2004.
[39] M. Sarkar, G. S. Taki, Prerna, R. Sengupta and S. N. Ray, "Design of ripple carry adder using CMOS output wired logic based majority gate," 2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON), Bangkok, 2017, pp. 328-331.
[40] M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman and S. Islam, "Design of a Scalable Low-Power 1-bit Hybrid Full Adder for Fast Computation," in IEEE Transactions on Circuits and Systems II: Express Briefs, 2019.
[41] H. Naseri and S. Timarchi, "Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1481-1493, Aug. 2018.
[42] M. Hasan, H. U. Zama, M. Hossain, P. Biswas, S. Islam, “Gate Diffusion Input technique based full swing and scalable 1-bit hybrid full adder for high performance applications,” Engineering Science and Technology, An International Journal, 2020.
[43] V. Foroutan, M. R. Taheri, K. Navi, A. A. Mazreah, “Design of two low-power full adder cells using GDI structure and hybrid CMOS logic style,” Integration, vol. 47, no. 1, pp. 48-61, 2014.
[44] M. Hasan, U. K. Saha, A. Sorwar, M. A. Z. Dipto, M. S. Hossain and H. U. Zaman, "A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic," 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Kanpur, India, 2019, pp. 1-6.
[45] B. R. Zeydel, D. Baran and V. G. Oklobdzija, "Energy-Efficient Design Methodologies: High-Performance VLSI Adders," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1220-1233, June 2010.
[46] S. Chandra, K. Lahiri, A. Raghunathan and S. Dey, "Variation-Tolerant Dynamic Power Management at the System-Level," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1220-1232, Sept. 2009.
[47] G.K. Reddy and S. B. Rao, “A comparative study on low-power and high speed Carry Select Adder,” 2015 IEEE 9th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, India.
[48] A.P. Thakare, S. Agrawal and V. Tiwari, “32 Bit Carry Select Adder with BEC-1 Technique,” Sixth IRAJ International Conference, 6th October 2013, Pune, India.
[49] Rashmi S.B and V. Oli, "32 bit power efficient carry select adder using 4T XNOR gate," 2016 2nd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT), Bangalore, 2016, pp. 283-287.
[50] S.Sakthikumaran,S.Salivahanan,V.S.KanchanaBhaaskaran,V.Kavinilavu , “A very fast and low power carry select adder circuit,” 2011 3rd International Conference on Electronics Computer Technology, Kanyakumari, India
[51] G.A. Ruiz, M. Granda, “An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit,” Microelectronics Journal, Volume 35, Issue 12, Pages 939-944, December 2004.
[52] S. Manju ,V. Sornagopal, “An efficient SQRT architecture of Carry Select adder design by Common Boolean logic,” 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), Tiruvannamalai, India
[53] S. Parmar , K.P. Singh, “Design of high speed hybrid carry select adder,” 2013 3rd IEEE International Advance Computing Conference (IACC), Ghaziabad, India
[54] Rahul C.G, N Saraswathi, “Implementation of an efficient 64-bit Carry Select Adder using Muxes,” 2014 IEEE International Conference on Advanced Communication Control and Computing Teclmologies (ICACCCT)
[55] B. Ramkumar and H. M Kittur, “Low-Power and Area-Efficient Carry Select Adder,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, NO. 2, February 2012